RESEARCH ARTICLES
Performance Evaluation of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems
Woonseok Kim, Dongkun Shin, Han-Saem Yun, Jihong Kim, and Sang Lyul Min
J. Low Power Electronics 1, 207–216 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Selective Clock-Gating for Low-Power Synchronous Counters
Arindam Calomarde, Antonio Rubio, and Jordi Saludes
J. Low Power Electronics 1, 217–225 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Energy-aware dynamic task scheduling applied to a real-time multimedia application on an Xscale board
Chantal Ykman-Couvreur, Francky Catthoor, Johan Vounckx, Andy Folens, and Filip Louagie
J. Low Power Electronics 1, 226–237 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator
Yan Meng, Wenrui Gong, Ryan Kastner, and Timothy Sherwood
J. Low Power Electronics 1, 238–248 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Trading Time and Space on Low Power Embedded Architectures with Dynamic Instruction Merging
Victor F. Gomes, Antônio Carlos S. Beck, and Luigi Carro
J. Low Power Electronics 1, 249–258 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits
Xiaoyong Tang, Tianyi Jiang, Alex Jones, and Prithviraj Banerjee
J. Low Power Electronics 1, 259–272 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Early Quality Assessment for Low Power Behavioral Synthesis
Eren Kursun, Rajarshi Mukherjee, and Seda Ogrenci Memik
J. Low Power Electronics 1, 273–285 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Implementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks
Dhireesha Kudithipudi and Eugene John
J. Low Power Electronics 1, 286–296 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Microarchitecture Level Interconnect Modeling Considering Layout Optimization
Weiping Liao and Lei He
J. Low Power Electronics 1, 297–308 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips
Mauro Olivieri, Simone Smorfa, and Alessandro Trifiletti
J. Low Power Electronics 1, 309–318 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Efficient Test Set Modification for Capture Power Reduction
Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, and Kewal K. Saluja
J. Low Power Electronics 1, 319–330 (2005)
[Abstract] [Full Text - PDF] [Purchase Article]

Table of Contents to Volume 1, Number 1–3, 2005
[Abstract] [Full Text - PDF] [Purchase Article]

Author Index to Volume 1, Number 1–3, 2005
[Abstract] [Full Text - PDF] [Purchase Article]

Subject Index to Volume 1, Number 1–3, 2005
[Abstract] [Full Text - PDF] [Purchase Article]

pp. 97–107 - Optimal Minimal-Skew Battery Lifetime Routing in Distributed Embedded Systems
Roozbeh Jafari, Foad Dabiri, and Majid Sarrafzadeh
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 108–118 Low Power Correlating Caches for Network Processors
Arindam Mallik and Gokhan Memik
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 119–132 On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays
Julien Lamoureux and Steven J. E. Wilton
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 133–144 A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect
Chang Woo Kang and Massoud Pedram
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 145–152 Pseudo Dual Supply Voltage Domino Logic Design
Abdulkadir U. Diril, Yuvraj S. Dhillon, Abhijit Chatterjee, and Adit D. Singh
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 153–160 A 1 V 270 µW 2 GHz CMOS Synchronized Ring Oscillator Based Prescaler
Olivier Mazouffre, Hervé Lapuyade, Jean-Baptiste Bégueret, Andreia Cathelin, Didier Belot, and Yann Deval
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 161–171 Arithmetic-Level Instruction Based Energy Estimation for FPGA based Soft Processors
Jingzhao Ou and Viktor K. Prasanna
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 172–181 Leakage and Leakage Sensitivity Computation for Combinational Circuits
Emrah Acar, Anirudh Devgan, and Sani R. Nassif
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 182–193 Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits
Praveen Elakkumanan, Kishan Prasad, and Ramalingam Sridhar
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp. 194–205 Low Power Test Generation for Path Delay Faults
M. M. Vaseekar Kumar and S. Tragoudas
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

RESEARCH ARTICLES
pp.3-10 An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth
Christian Schuster, Christian Piguet, Jean-Luc Nagel, and Pierre-André Farine
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp.11-19 Selective Clock-Gating for Low-Power Synchronous Counters
Pilar Parra, Antonio J. Acosta, Raúl Jiménez, and Manuel Valencia
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp.20-26 Compact and Secured Primitives for the Design of Asynchronous Circuits
A. Razafindraibe, M. Robert, and P. Maurine
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp.27-43 Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player
Kihwan Choi, Wei-Chung Cheng, and Massoud Pedram
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp.44-51 Energy-Aware MPEG-4 FGS Streaming
Kihwan Choi, Kwanho Kim, and Massoud Pedram
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp.52-62 Low-Energy Heterogeneous Non-Volatile Memory Systems for Mobile Systems
Hyung Gyu Lee and Naehyuck Chang
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp.63-72 Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits
Shalini Ghosh, Sugato Basu, and Nur A.Touba
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp.73-84 Power and Design for Test: A Design Automation Perspective
Aurelia De Colle, Sanjay Ramnath, Mokhtar Hirech, and Subramanian Chebiyam
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]

pp.85-95 Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing
Patrick Girard and Yannick Bonhomme
[Abstract] [Full Text - PDF] [Full Text - RealPage] [Purchase Article]