INVITED PAPERS
Low-Power Heterogeneous Systems-on-Chips
Christian Piguet, Jean-Luc Nagel, Vincent Peiris, Stève Gyger, Daniel Séverac, Marc Morgan, and
Jean-Marc Masgonty
J. Low Power Electronics 4, 111-126 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Test Strategies for Low-Power Devices
C. P. Ravikumar, M. Hirech, and X. Wen
J. Low Power Electronics 4, 127-138 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

RESEARCH ARTICLES
A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation
Sheldon X.-D. Tan, Pu Liu, Lin Jiang, Wei Wu, and Murli Tirumala
J. Low Power Electronics 4, 139-148 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Low Power Main Memory Configuration and Tasks Allocation
Hanene Ben Fradj, Cécile Belleudy, Michel Auguin, and Alain Pegatoquet
J. Low Power Electronics 4, 149-157 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM
A. Dandapat, D. Kayal, and D. Mukhopadhyay
J. Low Power Electronics 4, 158-168 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Fuzzy Control of Coding Schemes for Reducing Energy Dissipation in Off-Chip Buses
Giuseppe Visalli
J. Low Power Electronics 4, 169-177 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Differential Cascode Adiabatic Logic Structure for Low Power
V. S. Kanchana Bhaaskaran and J. P. Raina
J. Low Power Electronics 4, 178-190 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing
Tai-Hsuan Wu, Lin Xie, and Azadeh Davoodi
J. Low Power Electronics 4, 191-201 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Simple Single Time Constant Circuits Using Low Voltage Operational Floating Conveyor
T. Parveen and M. T. Ahmed
J. Low Power Electronics 4, 202-207 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter
D. Meganathan, S. Moorthi, Amrith Sukumaran, M. M. Dinesh Babu, and J. Raja Paul Perinbam
J. Low Power Electronics 4, 208-227 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Programmable Current Source Design Dedicated to an Advanced Cochlear Implant Micro-Stimulator
Neila Rekik, Sonda Shabou, Ahmed Ben Hamida, and Mounir Samet
J. Low Power Electronics 4, 228-239 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance
R. Srinivasan and Navakanta Bhat
J. Low Power Electronics 4, 240-246 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

INVITED PAPERS
Energy-Aware Task Scheduling and Dynamic Voltage Scaling in a Real-Time System
Peng Rong and Massoud Pedram
J. Low Power Electronics 4, 1–10 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Survey of Hardware Systems for Wireless Sensor Networks
Mark Hempstead, Michael J. Lyons, David Brooks, and Gu-Yeon Wei
J. Low Power Electronics 4, 11–20 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

RESEARCH ARTICLES
High-Level Interconnect Delay and Power Estimation
Antoine Courtay, Olivier Sentieys, Johann Laurent, and Nathalie Julien
J. Low Power Electronics 4, 21–33 (2008)
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Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays
Kostas Siozios, Dimitrios Soudris, and Antonios Thanailakis
J. Low Power Electronics 4, 34–47 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Design and Analysis of a Low Power Multi-Threshold CMOS Based ARM926 System
Sachin Idgunji and David Flynn
J. Low Power Electronics 4, 48–59 (2008)
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A Novel Low Power Oriented Design Methodology for Analog Blocks
Hassen Aziza, Emmanuel Bergeret, J.-Michel Portal, and Olivier Ginez
J. Low Power Electronics 4, 60–67 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory
Sarvesh Bhardwaj and Sarma Vrudhula
J. Low Power Electronics 4, 68–80 (2008)
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Low Power Test for Nanometer System-on-Chips (SoCs)
Srivaths Ravi, Rubin Parekhji, and Jayashree Saxena
J. Low Power Electronics 4, 81–100 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, and V. Kamakoti
J. Low Power Electronics 4, 101–110 (2008)
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