Journal of Low Power Electronics

Volume 4, Number 3 (December 2008) pp.247-446


RESEARCH ARTICLES
A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation
Felipe Machado, Yago Torroja, and Teresa Riesgo
J. Low Power Electronics 4, 247–262 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Hybrid-CV Modeling for Estimating the Variability in Dynamic Power
B. P. Harish, Navakanta Bhat, and Mahesh B. Patil
J. Low Power Electronics 4, 263–274 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs
Kostas Siozios and Dimitrios Soudris
J. Low Power Electronics 4, 275–289 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Power Gating Clustered Many-Core Architectures
Enric Musoll
J. Low Power Electronics 4, 290–300 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local
Variations Based on Transistor Stacks

Janakiraman Viraraghavan, Bharadwaj Amrutur, and V. Visvanathan
J. Low Power Electronics 4, 301–319 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in
the Sub-Threshold Regime

Omer Can Akgun and Yusuf Leblebici
J. Low Power Electronics 4, 320–336 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power
Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, and Scott Smith
J. Low Power Electronics 4, 337–348 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Design and Implementation of Low-Power Bloom Filters for Deep Packet Inspection
Michael Paynter and Taskin Kocak
J. Low Power Electronics 4, 349–359 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity
Jeremy Lee and Mohammad Tehranipoor
J. Low Power Electronics 4, 360–371 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

SPECIAL SECTION
Selected Peer-Reviewed Articles from the LPonTR 2008 Workshop
Guest Editors: Alex Bystrov and João Paulo Teixeira
J. Low Power Electronics 4, 372–373 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

RESEARCH ARTICLES
Thermal-Aware Design Techniques for Nanometer CMOS Circuits
A. Calimera, K. Duraisami, A. Sathanur, P. Sithambaram, R. I. Bahar, A. Macii, E. Macii, and M. Poncino
J. Low Power Electronics 4, 374–384 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems
Judit F. Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, and J. Paulo Teixeira
J. Low Power Electronics 4, 385–391 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Lithography Simulation Basics and a Study on Impact of Lithographic Process Window
on Gate and Path Delays

Aswin Sreedhar and Sandip Kundu
J. Low Power Electronics 4, 392–401 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Test Power Analysis at Register Transfer Level
Ivano Midulla and Chouki Aktouf
J. Low Power Electronics 4, 402–409 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Time Management for Low-Power Design of Digital Systems
Jorge Semião, Judit F. Freijedo, Juan J. Rodriguez-Andina, Fabian Vargas, Marcelino B. Santos,
Isabel C. Teixeira, and J. Paulo Teixeira

J. Low Power Electronics 4, 410–419 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A Scan Controller Concept for Low Power Scan Tests
Rene Kothe and Heinrich T. Vierhaus
J. Low Power Electronics 4, 420–428 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Functional Broadside Tests with Minimum and Maximum Switching Activity
Irith Pomeranz and Sudhakar M. Reddy
J. Low Power Electronics 4, 429–437 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Table of Contents to Volume 4, Number 1–3, 2008
J. Low Power Electronics 4, 439–440 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Author Index to Volume 4, Number 1–3, 2008
J. Low Power Electronics 4, 441–443 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Subject Index to Volume 4, Number 1–3, 2008
J. Low Power Electronics 4, 444–446 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Volume 4, Number 2 (August 2008) pp.111-246


INVITED PAPERS
Low-Power Heterogeneous Systems-on-Chips
Christian Piguet, Jean-Luc Nagel, Vincent Peiris, Stève Gyger, Daniel Séverac, Marc Morgan, and
Jean-Marc Masgonty

J. Low Power Electronics 4, 111-126 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Test Strategies for Low-Power Devices
C. P. Ravikumar, M. Hirech, and X. Wen
J. Low Power Electronics 4, 127-138 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

RESEARCH ARTICLES
A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation
Sheldon X.-D. Tan, Pu Liu, Lin Jiang, Wei Wu, and Murli Tirumala
J. Low Power Electronics 4, 139-148 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Low Power Main Memory Configuration and Tasks Allocation
Hanene Ben Fradj, Cécile Belleudy, Michel Auguin, and Alain Pegatoquet
J. Low Power Electronics 4, 149-157 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM
A. Dandapat, D. Kayal, and D. Mukhopadhyay
J. Low Power Electronics 4, 158-168 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Fuzzy Control of Coding Schemes for Reducing Energy Dissipation in Off-Chip Buses
Giuseppe Visalli
J. Low Power Electronics 4, 169-177 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Differential Cascode Adiabatic Logic Structure for Low Power
V. S. Kanchana Bhaaskaran and J. P. Raina
J. Low Power Electronics 4, 178-190 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing
Tai-Hsuan Wu, Lin Xie, and Azadeh Davoodi
J. Low Power Electronics 4, 191-201 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Simple Single Time Constant Circuits Using Low Voltage Operational Floating Conveyor
T. Parveen and M. T. Ahmed
J. Low Power Electronics 4, 202-207 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter
D. Meganathan, S. Moorthi, Amrith Sukumaran, M. M. Dinesh Babu, and J. Raja Paul Perinbam
J. Low Power Electronics 4, 208-227 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Programmable Current Source Design Dedicated to an Advanced Cochlear Implant Micro-Stimulator
Neila Rekik, Sonda Shabou, Ahmed Ben Hamida, and Mounir Samet
J. Low Power Electronics 4, 228-239 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance
R. Srinivasan and Navakanta Bhat
J. Low Power Electronics 4, 240-246 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Volume 4, Number 1 (April 2008) pp.1-110


INVITED PAPERS
Energy-Aware Task Scheduling and Dynamic Voltage Scaling in a Real-Time System
Peng Rong and Massoud Pedram
J. Low Power Electronics 4, 1–10 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Survey of Hardware Systems for Wireless Sensor Networks
Mark Hempstead, Michael J. Lyons, David Brooks, and Gu-Yeon Wei
J. Low Power Electronics 4, 11–20 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

RESEARCH ARTICLES
High-Level Interconnect Delay and Power Estimation
Antoine Courtay, Olivier Sentieys, Johann Laurent, and Nathalie Julien
J. Low Power Electronics 4, 21–33 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays
Kostas Siozios, Dimitrios Soudris, and Antonios Thanailakis
J. Low Power Electronics 4, 34–47 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Design and Analysis of a Low Power Multi-Threshold CMOS Based ARM926 System
Sachin Idgunji and David Flynn
J. Low Power Electronics 4, 48–59 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A Novel Low Power Oriented Design Methodology for Analog Blocks
Hassen Aziza, Emmanuel Bergeret, J.-Michel Portal, and Olivier Ginez
J. Low Power Electronics 4, 60–67 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory
Sarvesh Bhardwaj and Sarma Vrudhula
J. Low Power Electronics 4, 68–80 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

Low Power Test for Nanometer System-on-Chips (SoCs)
Srivaths Ravi, Rubin Parekhji, and Jayashree Saxena
J. Low Power Electronics 4, 81–100 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, and V. Kamakoti
J. Low Power Electronics 4, 101–110 (2008)
[Abstract] [Full Text - PDF] [Purchase Article]


Terms and Conditions  Privacy Policy  Copyright © 2000- American Scientific Publishers. All Rights Reserved.