RESEARCH ARTICLES
Energy Estimation of the Memory Subsystem in Multiprocessor Systems
Eric F. Weglarz, Kewal K. Saluja, and Mikko H. Lipasti
J. Low Power Electronics 2, 325–332 (2006)
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Low-Power Perceptron Branch Predictor
Kaveh Aasaraai and Amirali Baniasadi
J. Low Power Electronics 2, 333–341 (2006)
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System Wide Dynamic Power Management for Weakly Hard Real-Time Systems
Linwei Niu and Gang Quan
J. Low Power Electronics 2, 342–355 (2006)
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Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers
A. P. Kakarountas, N. D. Zervas, G. Theodoridis, H. E. Michail, and D. Soudris
J. Low Power Electronics 2, 356–364 (2006)
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An Effective Combinatorial Algorithm for Gate-Level Threshold Voltage Assignment
Soheil Ghiasi
J. Low Power Electronics 2, 365–377 (2006)
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CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff
Yuanlin Lu and Vishwani D. Agrawal
J. Low Power Electronics 2, 378–387 (2006)
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WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays
Mahadevan Gomathisankaran and AkhileshTyagi
J. Low Power Electronics 2, 388–400 (2006)
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SRAM Cell Optimization for Ultra-Low Power Standby
Huifang Qin, Rakesh Vattikonda, Thuan Trinh, Yu Cao, and Jan Rabaey
J. Low Power Electronics 2, 401–411 (2006)
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Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power
Sayeed A. Badrudduza, Giby Samson, and Lawrence T. Clark
J. Low Power Electronics 2, 412–424 (2006)
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Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses
K. Najeeb, Vishal Gupta, V. Kamakoti, and Madhu Mutyam
J. Low Power Electronics 2, 425–436 (2006)
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Low-Power CMOS Ramp Generator Circuit for DC-DC Converters
H. Pooya Forghani-zadeh and Gabriel A. Rincón-Mora
J. Low Power Electronics 2, 437–441 (2006)
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An Advanced Low Power and Versatile CMOS Current Driver for Multi-Electrode Cochlear Implant Microstimulator
Mohamed Ghorbel, Ahmed Ben Hamida, Mounir Samet, and Jean Thomas
J. Low Power Electronics 2, 442–455 (2006)
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Defect Tolerant Voter Designs Based on Transistor Redundancy
Z. Abid and H. El-Razouk
J. Low Power Electronics 2, 456–463 (2006)
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On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores
V. R. Devanathan, C. P. Ravikumar, and V. Kamakoti
J. Low Power Electronics 2, 464–476 (2006)
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Scan-Based Structure with Reduced Static and Dynamic Power Consumption
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, and Zainalabedin Navabi
J. Low Power Electronics 2, 477–487 (2006)
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Table of Contents to Volume 2, Number 1–3, 2006
J. Low Power Electronics 2, 489–491 (2006)
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Author Index to Volume 2, Number 1–3, 2006
J. Low Power Electronics 2, 492–495 (2006)
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Subject Index to Volume 2, Number 1–3, 2006
J. Low Power Electronics 2, 496–498 (2006)
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GENERAL RESEARCH ARTICLE
A Fast, Dynamic, Fine-Detail, Source Level Technique to Estimate the Energy Consumed by
Embedded Software on Single-Issue Processor Cores
Daniele Paolo Scarpazza and Carlo Brandolese
J. Low Power Electronics 2, 129–139 (2006)
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Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing
Bramha Allu and Wei Zhang
J. Low Power Electronics 2, 140–147 (2006)
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A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture
Gayatri Mehta, Justin Stander, Josh Lucas, Raymond R. Hoare, Brady Hunsaker, and Alex K. Jones
J. Low Power Electronics 2, 148–164 (2006)
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Communication Power Optimization for Network-on-Chip Architectures
Dongkun Shin and Jihong Kim
J. Low Power Electronics 2, 165–176 (2006)
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Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power
Yangdong (Steven) Deng and Peng Li
J. Low Power Electronics 2, 177–188 (2006)
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An Efficient Assignment of Voltages and Optional Cycles for Maximizing Rewards in
Real-Time Systems with Energy Constraints
Ali Mahdoum, Nadjib Badache, and Hamid Bessalah
J. Low Power Electronics 2, 189–200 (2006)
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Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design
Jia Di and J. S. Yuan
J. Low Power Electronics 2, 201–216 (2006)
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Power Distribution Techniques for Dual VDD Circuits
Sarvesh H. Kulkarni and Dennis Sylvester
J. Low Power Electronics 2, 217–229 (2006)
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Gate Sizing and V_t Assignment for Active-Mode Leakage Power Reduction
Feng Gao and John P. Hayes
J. Low Power Electronics 2, 230–239 (2006)
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Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, and Threshold Voltage Selection
Sarvesh Bhardwaj, Yu Cao, and Sarma Vrudhula
J. Low Power Electronics 2, 240–250 (2006)
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Subthreshold to Above Threshold Level Shifter Design
Tai-Hua Chen, Jinhui Chen, and Lawrence T. Clark
J. Low Power Electronics 2, 251–258 (2006)
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Power Optimized Design of CMOS Programmable Gain Amplifiers
Srikanth Mohan, Arun Ravindran, David Binkley, and Arindam Mukherjee
J. Low Power Electronics 2, 259–270 (2006)
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Reducing Power Dissipation in SRAM during Test
Luigi Dilillo, Paul Rosinger, Bashir M. Al-Hashimi, and Patrick Girard
J. Low Power Electronics 2, 271–280 (2006)
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SELECTED PEER-REVIEWED RESEARCH ARTICLES FROM THE DCIS 2005 CONFERENCE
João Paulo Teixeira, José Silva Matos, and Jean Tomas, Guest Editors
J. Low Power Electronics 2, (2006)
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Software Level Power Consumption Models and Power Saving Techniques for Embedded
DSP Processors
C. J. Bleakley, Miguel Casas-Sanchez, and Jose Rizo-Morente
J. Low Power Electronics 2, 281–290 (2006)
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Multiclock Domain and Dynamic Frequency Scaling Applied to the Control Unit of a
Battery Powered for 1 cm³ Microrobot
Raimon Casanova, Angel Dieguez, Anna Arbat, and Josep Samitier
J. Low Power Electronics 2, 291–299 (2006)
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Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for
Low Power Applications
Victor Navarro-Botello, Juan A. Montiel-Nelson, and Saeid Nooshabadi
J. Low Power Electronics 2, 300–307 (2006)
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Low-Voltage Low-Power Broadband CMOS Analogue Circuit for White Gaussian Noise Generation
Guiomar Evans, João Goes, and Nuno Paulino
J. Low Power Electronics 2, 308–316 (2006)
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Super Class AB OTAs Based on Low-Power Adaptive Techniques at the Input Stage
and the Active Load
J. Galan, Ramón G. Carvajal, J. Ramírez-Angulo, Antonio J. López-Martín, and C. Rubia-Marcos
J. Low Power Electronics 2, 317–324 (2006)
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GENERAL RESEARCH ARTICLE
Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold
Voltage Variation
Wei-Shen Wang, Michael Liu, and Michael Orshansky
J. Low Power Electronics 2, 1–7 (2006)
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SELECTED PEER-REVIEWED RESEARCH ARTICLES from the PATMOS 2005 Workshop
GUEST EDITORS: Johan Vounckx and Vassilis Paliouras,
J. Low Power Electronics 2 (2006)
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Systematic Preprocessing of Data Dependent Constructs for Embedded Systems
Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, and Francky Catthoor
J. Low Power Electronics 2, 9–17 (2006)
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Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz
WLAN Applications
Labros Bisdounis, Spyridon Blionas, Enrico Macii, Spiridon Nikolaidis, and Roberto Zafalon
J. Low Power Electronics 2, 18–26 (2006)
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A Load-Store Queue Design Based on Predictive State Filtering
Fernando Castro, Daniel Chaver, Luis Pinuel, Manuel Prieto, Michael C. Huang, and Francisco Tirado
J. Low Power Electronics 2, 27–36 (2006)
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Back-Annotation in High-Speed Asynchronous Design
Pankaj Golani and Peter A. Beerel
J. Low Power Electronics 2, 37–44 (2006)
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On the use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits
David Rios-Arambula, Aurelien Buhrig, Gilles Sicard, and Marc Renaudin
J. Low Power Electronics 2, 45–55 (2006)
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Analysis and Optimization of MPSoC Reliability
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kresimir Mihic, Giovanni De Micheli, and Yusuf Leblebici
J. Low Power Electronics 2, 56–69 (2006)
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Energy-Efficient Value Based Selective Refresh for Embedded DRAMS
Kimish Patel, Enrico Macii, Massimo Poncino, and Luca Benini
J. Low Power Electronics 2, 70–79 (2006)
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An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits
Josep Rius, Maurice Meijer, and José Pineda de Gyvez
J. Low Power Electronics 2, 80–86 (2006)
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Accurate Logic-Level Current Estimation for Digital CMOS Circuits
P. Ruiz-de-Clavijo, J. Juan-Chico, M. J. Bellido, A. Millán, D. Guerrero, E. Ostúa, and J. Viejo
J. Low Power Electronics 2, 87–94 (2006)
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Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
Philippe Manet, Renaud Ambroise, David Bol, Marc Baltus, and Jean-Didier Legat
J. Low Power Electronics 2, 95–104 (2006)
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Power Supply Selective Mapping for Accurate Timing Analysis
Cristiano Forzan, Davide Pandini, and Mariagrazia Graziano
J. Low Power Electronics 2, 105–112 (2006)
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Power – Performance Optimization for Custom Digital Circuits
Radu Zlatanovici and Borivoje Nikolic
J. Low Power Electronics 2, 113–120 (2006)
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Transistor Sizing of Logic Gates to Maximize Input Delay Variability
Tezaswi Raja, Vishwani D. Agrawal, and Michael L. Bushnell
J. Low Power Electronics 2, 121–128 (2006
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