RESEARCH ARTICLES
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder
Sohan Purohit, Marco Lanuzza, and Martin Margala
J. Low Power Electron. 6, 469-481 (2010)
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Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique
Kiran K. Chaddha and Rajeevan Chandel
J. Low Power Electron. 6, 482-490 (2010)
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Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect
Ying Teng and Baris Taskin
J. Low Power Electron. 6, 491-502 (2010)
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Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR
Circuits in Hybrid-CMOS Logic Style
Tooraj Nikoubin, Mahdieh Grailoo, and Sayyed Hasan Mozafari
J. Low Power Electron. 6, 503-512 (2010)
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Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications
Ashutosh Nandi and Rajeevan Chandel
J. Low Power Electron. 6, 513-520 (2010)
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Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation
Maurice Meijer, José Pineda de Gyvez, and Ajay Kapoor
J. Low Power Electron. 6, 521-532 (2010)
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Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control
S. S. Rathod, A. K. Saxena, and S. Dasgupta
J. Low Power Electron. 6, 533-544 (2010)
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Low Power Radio Frequency Identification Design Using Custom Asynchronous Passive Computer
Vyasa Sai, Ajay Ogirala, and Marlin H. Mickle
J. Low Power Electron. 6, 545-550 (2010)
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A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder
Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, and Wei Hwang
J. Low Power Electron. 6, 551-562 (2010)
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A SPECIAL SECTION
Selected Peer-Reviewed Articles from the VARI 2010 Workshop
Guest Editor: Nadine Azemard
J. Low Power Electron. 6, 563 (2010)
[Abstract] [Full Text - PDF] [Purchase Article]

RESEARCH ARTICLES
Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips
Imen Mansouri, Pascal Benoit, Diego Puschini, Lionel Torres, Fabien Clermidy, and Gilles Sassatelli
J. Low Power Electron. 6, 564-577 (2010)
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Statistical Moment Estimation of Delay and Power in Circuit Simulation
Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, and Nick van der Meijs
J. Low Power Electron. 6, 578-587 (2010)
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Lithography Aware Regular Cell Design Based on a Predictive Technology Model
Sergio Gómez and Francesc Moll
J. Low Power Electron. 6, 588-600 (2010)
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On-Chip Process Variability Monitoring Flow
Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azemard, Vincent Dumettier, and
Pierre Busson
J. Low Power Electron. 6, 601-606 (2010)
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Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization
Nikos Andrikos, Luciano Lavagno, Fabio Campi, and Davide Pandini
J. Low Power Electron. 6, 607-615 (2010)
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Table of Contents to Volume 6, Number 1-4, 2010
J. Low Power Electron. 6, 617-619 (2010)
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Author Index to Volume 6, Number 1-4, 2010
J. Low Power Electron. 6, 620-624 (2010)
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Subject Index to Volume 6, Number 1-4, 2010
J. Low Power Electron. 6, 625-627 (2010)
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A SPECIAL ISSUE
A Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010
Guest Editor: Swarup Bhunia
J. Low Power Electron. 6, 375 (2010)
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RESEARCH ARTICLES
Power Aware High Level Synthesis of Hardware Coprocessors
Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, and Sandeep K. Shukla
J. Low Power Electron. 6, 376-389 (2010)
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DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM
Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, and Elias Kougianos
J. Low Power Electron. 6, 390-400 (2010)
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Design of Low Power Systems Using Inexact Logic Circuits
R. Bharghava, R. Abinesh, Suresh Purini, and R. Govindatajulu
J. Low Power Electron. 6, 401-414 (2010)
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Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated
Logic Circuits
Vinay Saripalli, Lu Liu, Suman Datta, and Vijaykrishnan Narayanan
J. Low Power Electron. 6, 415-428 (2010)
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An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects
Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, and M. B. Srinivas
J. Low Power Electron. 6, 429-435 (2010)
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A Novel Threshold Voltage Assignment for 3D Multicore Designs
Koushik Chakraborty and Sanghamitra Roy
J. Low Power Electron. 6, 436-446 (2010)
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Tuning Vth Hopping for Aggressive Runtime Leakage Control
Hao Xu, Wen-Ben Jone, and Ranga Vemuri
J. Low Power Electron. 6, 447-456 (2010)
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PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture
Zhen Chen, Sharad C. Seth, Dong Xiang, and Bhargab B. Bhattacharya
J. Low Power Electron. 6, 457-468 (2010)
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RESEARCH ARTICLES
A Markovian Decision-Based Approach for Extending the Lifetime of a Network of
Battery-Powered Mobile Devices by Remote Processing
Peng Rong and Massoud Pedram
J. Low Power Electron. 6, 227–239 (2010)
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Design and Analysis of Location Caches in a NoC-Based Chip Multiprocessor System
D. Ramakrishnan, Y. L. Wu, and W. B. Jone
J. Low Power Electron. 6, 240–262 (2010)
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Low-Leakage and Compact Registers with Easy-Sleep Mode
Hailong Jiao and Volkan Kursun
J. Low Power Electron. 6, 263–279 (2010)
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Power-Yield Enhancement for Field Programmable Gate Arrays Under Process Variations
Akhilesh Kumar and Mohab Anis
J. Low Power Electron. 6, 280–290 (2010)
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Charge Recycling in Voltage-Dithered Circuits
Thomas Schweizer, Julio Oliveira, Tommy Kuhn, and Wolfgang Rosenstiel
J. Low Power Electron. 6, 291–299 (2010)
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Low-Power Circuit Techniques for Charge-Scaling Successive Approximation Register ADC Design
Mallik Kandala and Haibo Wang
J. Low Power Electron. 6, 300–310 (2010)
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Scan Shift Power Reduction by Gating Internal Nodes
Dheepakkumaran Jayaraman, Rajamani Sethuram, and Spyros Tragoudas
J. Low Power Electron. 6, 311–319 (2010)
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COMMUNICATION
Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime
David Coleman and Jia Di
J. Low Power Electron. 6, 320–324 (2010)
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A SPECIAL SECTION
Selected Peer-Reviewed Articles from the LPonTR 2009 Workshop
Guest Editor: Alex Bystrov
J. Low Power Electron. 6, 325 (2010)
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RESEARCH ARTICLES
Power Supply Noise: Causes, Effects, and Testing
Ilia Polian
J. Low Power Electron. 6, 326–338 (2010)
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Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance
J. Freijedo, L. Costas, J. Semião, J. J. Rodríguez-Andina, M. J. Moure, F. Vargas, I. C. Teixeira, and J. P. Teixeira
J. Low Power Electron. 6, 339–349 (2010)
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Test Sequences with Reduced and Increased Switching Activity
Irith Pomeranz and Sudhakar M. Reddy
J. Low Power Electron. 6, 350–358 (2010)
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A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for
Launch-Off-Shift and Launch-Off-Capture Schemes
F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, X. Wen, and N. Ahmed
J. Low Power Electron. 6, 359–374 (2010)
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PEER-REVIEWED RESEARCH ARTICLES
An Efficient Energy Estimation Methodology for Quasi Delay Insensitive Template-Based
Asynchronous Circuits
Behnam Ghavami, Hossein Pedram, and Mahtab Niknahad
J. Low Power Electron. 6, 1-9 (2010)
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Impact of Operating System Behavior on Battery Life
Binu P. John, Abhishek Agrawal, Bob Steigerwald, and Eugene B. John
J. Low Power Electron. 6, 10-17 (2010)
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State Space Reconfigurability: A Low Energy Implementation Architecture for Self Modifying Finite Automata
Ka-Ming Keung and Akhilesh Tyagi
J. Low Power Electron. 6, 18-31 (2010)
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Spatial Switching Data Coding Technique Analysis and Improvements for Interconnect Power
Consumption Optimization
Antoine Courtay, Johann Laurent, and Olivier Sentieys
J. Low Power Electron. 6, 32-43 (2010)
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A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits
L. Benini, A. Bocca, A. Bonanno, A. Macii, E. Macii, J. L. Nagel, C. Piguet, and M. Poncino
J. Low Power Electron. 6, 44-55 (2010)
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Characterization of Variation Aware Nanoscale Static Random Access Memory Designs
Sreeharsha Tavva and Dhireesha Kudithipudi
J. Low Power Electron. 6, 56-65 (2010)
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Robust SRAM Design via Joint Sizing and Voltage Optimization Under Dynamic Stability Constraints
Akshit Dayal, Peng Li, and Garng M. Huang
J. Low Power Electron. 6, 66-79 (2010)
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A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis
Under Effective Channel-Length Variation
Sudip Roy and Ajit Pal
J. Low Power Electron. 6, 80-92 (2010)
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Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep
Sub-Micron Technologies
Alejandro Millan, Manuel J. Bellido, Jorge Juan, David Guerrero, Paulino Ruiz-de-Clavijo, and Julian Viejo
J. Low Power Electron. 6, 93-102 (2010)
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Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs
Ramesh Vaddi, S. Dasgupta, and R. P. Agarwal
J. Low Power Electron. 6, 103-114 (2010)
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Exploring Circuit Adaptation for Yield Optimization of Low-Power All-Digital Phase-Locked Loops
Guo Yu and Peng Li
J. Low Power Electron. 6, 115-125 (2010)
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A 1.9 W Transient-Enhanced Low-Dropout Regulator with Voltage-Spike Suppression
Ka Nang Leung, Felix Kok Man Cheung, Marco Ho, Hiu Ching Poon, and Pui Ying Or
J. Low Power Electron. 6, 126-132 (2010)
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A High Power Switch-Mode LED Driver with an Efficient Current Sensing Scheme
Wing Yan Leung, Tsz Yin Man, Dongwei Zhang, Jin He, and Mansun Chan
J. Low Power Electron. 6, 133-140 (2010)
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RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology
Ka Nang Leung, Chiu Sing Choy, Kong-Pang Pun, Lincoln Lai Kan Leung, Jianping Guo, Yuen Sum Ng,
Chi Fat Chan, Weiwei Shi, Yang Hong, Marco Ho, Ki-Leung Mak, and Yanqing Ai
J. Low Power Electron. 6, 141-149 (2010)
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A Novel IR-Drop Tolerant Transition Delay Fault Test Pattern Generation Procedure
Nisar Ahmed and Mohammad Tehranipoor
J. Low Power Electron. 6, 150-159 (2010)
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A SPECIAL SECTION
Selected Articles from the PATMOS 2009 Workshop
Guest Editor: José Monteiro
J. Low Power Electron. 6, 160 (2010)
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RESEARCH ARTICLES
Robust Low Power Embedded SRAM: From System Considerations to Cell Design
Toby Doorn and Roelof Salters
J. Low Power Electron. 6, 161-172 (2010)
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The Effect of Dynamic Power Management on Mid-Frequency and Low-Frequency Power Supply Noise
Howard Chen, Indira Nair, and Benjamin Mashak
J. Low Power Electron. 6, 173-180 (2010)
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Reducing Electromagnetic Interference Using Globally Asynchronous Locally Synchronous Approach
Miloš Krsti?, Tomasz Król, Xin Fan, and Eckhard Grass
J. Low Power Electron. 6, 181-191 (2010)
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Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits
Paulo F. Butzen, Vinícius Dal Bem, André I. Reis, and Renato P. Ribas
J. Low Power Electron. 6, 192-200 (2010)
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An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC
Using a 65-nm Standard CMOS Logic Process
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, and Amara Amara
J. Low Power Electron. 6, 201-210 (2010)
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Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits
Armin Tajalli and Yusuf Leblebici
J. Low Power Electron. 6, 211-217 (2010)
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Low-Power Soft Error Hardened Latch
Hossein Karimiyan Alidash and Vojin G. Oklobdzija
J. Low Power Electron. 6, 218-226 (2010)
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