Journal of Low Power Electronics

Volume 3, Number 3 (December 2007) pp.223-362


INVITED PAPERS
Exploring Very Low-Energy Logic: A Case Study
L. P. Alarcón, T.-T. Liu, M. D. Pierson, and J. M. Rabaey
J. Low Power Electronics 3, 223–233 (2007)
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Low Power and Energy Efficient Asynchronous Design
Peter A. Beerel and Marly E. Roncken
J. Low Power Electronics 3, 234–253 (2007)
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Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing
Nilanjan Banerjee and Kaushik Roy
J. Low Power Electronics 3, 254–270 (2007)
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RESEARCH ARTICLES
Architectural Power Analysis for Intellectual Property-Based Digital System
Yaseer A. Durrani and Teresa Riesgo
J. Low Power Electronics 3, 271–279 (2007)
[Abstract] [Full Text - PDF] [Purchase Article]

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits
K. Najeeb, Karthik Gururaj, V. Kamakoti, and Vivekananda M. Vedula
J. Low Power Electronics 3, 280–292 (2007)
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Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells
Dhireesha Kudithipudi and Eugene John
J. Low Power Electronics 3, 293–301 (2007)
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Energy-Efficient Techniques for Disk-Based Mobile Systems
Young-Jin Kim and Jihong Kim
J. Low Power Electronics 3, 302–317 (2007)
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Timing-Aware Power Minimization via Extended Timing Graph Methods
Haifeng Qian and Emrah Acar
J. Low Power Electronics 3, 318–326 (2007)
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A Low Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users
George N. Selimis, Athanasios P. Kakarountas, Apostolos P. Fournaris, Athanasios Milidonis, and
Odysseas Koufopavlou

J. Low Power Electronics 3, 327–336 (2007)
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Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects
Rajeevan Chandel, Sankar Sarkar, and Ashwani Chandel
J. Low Power Electronics 3, 337–344 (2007)
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Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits
Armin Tajalli, Paul Muller, and Yusuf Leblebici
J. Low Power Electronics 3, 345–354 (2007)
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Table of Contents to Volume 3, Number 1–3, 2007
J. Low Power Electronics 3, 355–356 (2007)
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Author Index to Volume 3, Number 1–3, 2007
J. Low Power Electronics 3, 357–359 (2007)
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Subject Index to Volume 3, Number 1–3, 2007
J. Low Power Electronics 3, 360–362 (2007)
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Volume 3, Number 2 (August 2007)


RESEARCH ARTICLES
Lethargic Cache: A Low Leakage Direct Mapped Cache
Nagm Mohamed, Adil Akaaboune and Nazeih Botros
J. Low Power Electronics 3, 119–123 (2007)
[Abstract] [Full Text - PDF] [Purchase Article]

A Measurement-based Automatic Energy Optimization Technique for Embedded Applications
Woongki Baek, Young-Jin Kim, Jinhyo Kim and Jihong Kim
J. Low Power Electronics 3, 124–132 (2007)
[Abstract] [Full Text - PDF] [Purchase Article]

An Ultra-Low Power Data Aggregation System for Wireless Micro sensor Networks
Giuseppe Visalli and Elio Guidetti
J. Low Power Electronics 3, 133–140 (2007)
[Abstract] [Full Text - PDF] [Purchase Article]

Simulated Annealing Based Temperature Aware Floorplanning
Yongkui Han and Israel Koren
J. Low Power Electronics 3, 141–155 (2007)
[Abstract] [Full Text - PDF] [Purchase Article]

Techniques for Power-aware Hardware Synthesis from Concurrent Action Oriented Specifications
Gaurav Singh, Jacob B. Schwartz, Sumit Ahuja and Sandeep K. Shukla
J. Low Power Electronics 3, 156–166 (2007)
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Precision Low Voltage and Current References
Brajesh Pandey and A. N. Chandorkar
J. Low Power Electronics 3, 167–174 (2007)
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Novel Adaptive Body Biasing Techniques for Energy Efficient Subthreshold CMOS Circuits
Walid M. Elgharbawy, Pradeep Golconda, Abdelhamid G. Moursy and Magdy A. Bayoumi
J. Low Power Electronics 3, 175–188 (2007)
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Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems
Alberto García-Ortiz, Tudor Murgan and Manfred Glesner
J. Low Power Electronics 3, 189–198 (2007)
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DFT MAX and Power
R. Kapur, T. Finklea, F. Ng, A. Chandra, S. Ramnath, P. Wohl, T.W. Williams, A. Anbalan, S. Kulkarni,
T. Fernandes, P. Notiyath and R. Uppuluri

J. Low Power Electronics 3, 199–205 (2007)
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Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing
Chun-Yi Lee and James Chien-Mo Li
J. Low Power Electronics 3, 206–216 (2007)
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SHORT PAPERS
Evaluation of an Adaptive Dynamic Voltage Scaling scheme for hard real-time applications
Craig A. Dolwin and Hatem Yassine
J. Low Power Electronics 3, 217–221 (2007)
[Abstract] [Full Text - PDF] [Purchase Article]

Volume 3, Number 1 (April 2007) pp.1-118


RESEARCH ARTICLES
Estimation of Leakage Power Consumption and Parametric Yield Based on
Realistic Probabilistic Descriptions of Parameters

Wei-Shen Wang and Michael Orshansky
J. Low Power Electronics 3, 1–12 (2007)
[Abstract] [Full Text - PDF] [Purchase Article]

TILTS: A Fast Architectural-Level Transient Thermal Simulation Method
Yongkui Han, Israel Koren, and C. M. Krishna
J. Low Power Electronics 3, 13–21 (2007)
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Heuristic on a Novel Power Management System Cooperating with Compiler
Xu Yang, Hu He, Zhixiong Zhou, Yanjun Zhang, and Yihe Sun
J. Low Power Electronics 3, 22–27 (2007)
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Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce
Anand Ramalingam, Anirudh Devgan, and David Z. Pan
J. Low Power Electronics 3, 28–35 (2007)
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A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing
Giuseppe Notarangelo, Francesco Pappalardo, Elena Salurso, and Elio Guidetti
J. Low Power Electronics 3, 36–42 (2007)
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Exploiting Speculation Cost Prediction in Power-Aware Applications
Ehsan Atoofian, Amirali Baniasadi, and Kaveh Aasaraai
J. Low Power Electronics 3, 43–53 (2007)
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Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process
Joachim Fenkes, Tobias Gemmeke, and Jens Leenstra
J. Low Power Electronics 3, 54–59 (2007)
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Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters
Steven D. Tucker, Arun Ravindran, Christopher Wichman, and Arindam Mukherjee
J. Low Power Electronics 3, 60–69 (2007)
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Improving the Performance of Static CMOS Gates by Using Independent Bodies
D. Guerrero, A. Millan, J. Juan, M. J. Bellido, P. Ruiz-de-Clavijo, E. Ostua, and J. Viejo
J. Low Power Electronics 3, 70–77 (2007)
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Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, and Abhijit Chatterjee
J. Low Power Electronics 3, 78–95 (2007)
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RFID Systems: Passive versus Active and a Novel Low-Power RF Transceiver for
IEEE 802.15.4 (ZigBee) Standard Based Applications

Domenico Zito, Domenico Pepe, and Bruno Neri
J. Low Power Electronics 3, 96–105 (2007)
[Abstract] [Full Text - PDF] [Purchase Article]

Low-Power Hierarchical Scan Test for Multiple Clock Domains
T. Senthil Arasu, C. P. Ravikumar, and S. K. Nandy
J. Low Power Electronics 3, 106–118 (2007)
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