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Vol. 1, No. 1
Vol. 1, No. 2
Vol. 1, No. 3
Vol. 2, No. 1
Vol. 2, No. 2
Vol. 2, No. 3
Titles
in Nanotechnology
Book Series
Encyclopedia of Nanoscience
and
Nanotechnology
Vols. 1-10
2005
Best Reference
Work Award
Handbook of Theoretical and
Computational
Nanotechnology
Vols. 1-10
Handbook of Semiconductor
Nanostructures
and Nanodevices
Vols. 1-5
Handbook of Nanostructured
Biomaterials and Their Applications
in Nanobiotechnology,
Vols. 1-2
Polymeric Nanostructures
and Their
Applications
Vols. 1-2
Handbook of Organic-Inorganic
Hybrid
Materials and
Nanocomposites, Vols. 1-2
Functional Nanomaterials
Molecular Nanoelectronics
Magnetic Nanostructures
Quantum Dots and Nanowires
Synthesis, Functionalization
and Surface Treatment
of Nanoparticles
Nanoclusters and Nanocrystals
Nanoscale Science and Engineering
Education
Bottom-up Nanofabrication
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Journal
of Low Power Electronics
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Vol.
4, No.1 |
Vol.
4, No.2 |
Vol.
4, No.3 |
Vol.
5, No.1 |
Vol.
5, No.2 |
Vol.
5, No.3 |
Vol.
5, No.4 |
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2009, Volume 5
Volume
5, Number 4 (December 2009)
Volume
5, Number 3 (October 2009)
Volume
5, Number 2 (August 2009)
Volume
5, Number 1 (April 2009)
2008, Volume 4
Volume
4, Number 3 (December 2008)
Volume
4, Number 2 (August 2008)
Volume
4, Number 1 (April 2008)
2007, Volume 3
Volume
3, Number 3 (December 2007)
Volume
3, Number 2 (August 2007)
Volume
3, Number 1 (April 2007)
2006, Volume 2
Volume
2, Number 3 (December 2006)
Volume
2, Number 2 (August 2006)
Volume
2, Number 1 (April 2006)
2005, Volume 1
Volume
1, Number 3 (December 2005)
Volume
1, Number 2 (August 2005)
Volume
1, Number 1 (April 2005)
| Volume
1, Number 3 (December 2005) |
RESEARCH ARTICLES
Performance
Evaluation of Dynamic Voltage Scaling Algorithms for Hard
Real-Time Systems
Woonseok
Kim, Dongkun Shin, Han-Saem Yun, Jihong Kim, and Sang Lyul Min
J.
Low Power Electronics 1, 207–216 (2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Selective Clock-Gating for
Low-Power Synchronous Counters
Arindam
Calomarde, Antonio Rubio, and Jordi Saludes
J. Low
Power Electronics 1, 217–225 (2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Energy-aware dynamic task
scheduling applied to a real-time multimedia application on an
Xscale board
Chantal
Ykman-Couvreur, Francky Catthoor, Johan Vounckx, Andy Folens,
and Filip Louagie
J. Low Power Electronics 1, 226–237
(2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Algorithm/Architecture
Co-exploration for Designing Energy Efficient Wireless Channel
Estimator
Yan Meng, Wenrui Gong, Ryan Kastner, and
Timothy Sherwood
J. Low Power Electronics 1, 238–248
(2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Trading Time and Space on Low
Power Embedded Architectures with Dynamic Instruction Merging
Victor
F. Gomes, Antônio Carlos S. Beck, and Luigi Carro
J.
Low Power Electronics 1, 249–258 (2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
High-Level
Synthesis for Low Power Hardware Implementation of Unscheduled
Data-Dominated Circuits
Xiaoyong Tang, Tianyi
Jiang, Alex Jones, and Prithviraj Banerjee
J. Low
Power Electronics 1, 259–272 (2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Early Quality
Assessment for Low Power Behavioral Synthesis
Eren
Kursun, Rajarshi Mukherjee, and Seda Ogrenci Memik
J.
Low Power Electronics 1, 273–285 (2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Implementation of
Low Power Digital Multipliers using 10 -Transistor Adder
Blocks
Dhireesha Kudithipudi and Eugene John
J.
Low Power Electronics 1, 286–296 (2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Microarchitecture
Level Interconnect Modeling Considering Layout Optimization
Weiping
Liao and Lei He
J. Low Power Electronics 1, 297–308
(2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Design and Test
of a Novel Programmable Clock Generator Semi-Custom Core for
Energy-Efficient Systems-on-Chips
Mauro Olivieri,
Simone Smorfa, and Alessandro Trifiletti
J. Low Power
Electronics 1, 309–318 (2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Efficient Test
Set Modification for Capture Power Reduction
Xiaoqing
Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro
Minamoto, Laung-Terng Wang, and Kewal K. Saluja
J.
Low Power Electronics 1, 319–330 (2005)
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Table of Contents
to Volume 1, Number 1–3, 2005
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Author Index to
Volume 1, Number 1–3, 2005
[Abstract]
[Full
Text - PDF] [Purchase
Article]
Subject Index to
Volume 1, Number 1–3, 2005
[Abstract]
[Full
Text - PDF] [Purchase
Article]
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Volume
1, Number 2 (August 2005) |
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RESEARCH ARTICLES
pp. 97–107  -
Optimal Minimal-Skew Battery Lifetime Routing in Distributed
Embedded Systems
Roozbeh Jafari, Foad Dabiri, and Majid
Sarrafzadeh
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 108–118 Low Power
Correlating Caches for Network Processors
Arindam
Mallik and Gokhan Memik
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 119–132 On the Interaction
between Power-Aware Computer-Aided Design Algorithms for
Field-Programmable Gate Arrays
Julien Lamoureux and
Steven J. E. Wilton
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 133–144 A Leakage-aware Low
Power Technology Mapping Algorithm Considering the Hot-Carrier
Effect
Chang Woo Kang and Massoud Pedram
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 145–152 Pseudo Dual Supply
Voltage Domino Logic Design
Abdulkadir U. Diril,
Yuvraj S. Dhillon, Abhijit Chatterjee, and Adit D. Singh
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 153–160 A 1 V 270 µW 2
GHz CMOS Synchronized Ring Oscillator Based Prescaler
Olivier
Mazouffre, Hervé Lapuyade, Jean-Baptiste Bégueret,
Andreia Cathelin, Didier Belot, and Yann Deval
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 161–171 Arithmetic-Level
Instruction Based Energy Estimation for FPGA based Soft Processors
Jingzhao Ou and Viktor K. Prasanna
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 172–181 Leakage and Leakage
Sensitivity Computation for Combinational Circuits
Emrah
Acar, Anirudh Devgan, and Sani R. Nassif
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 182–193 Low Power SER
Tolerant Design to Mitigate Single Event Transients in Nanoscale
Circuits
Praveen Elakkumanan, Kishan Prasad, and
Ramalingam Sridhar
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp. 194–205 Low Power Test
Generation for Path Delay Faults
M. M. Vaseekar Kumar
and S. Tragoudas
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article] |
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Volume
1, Number 1 (April 2005) |
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EDITORIAL
pp.1-2 Welcome to
the Journal of Low Power Electronics
Patrick Girard
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
RESEARCH ARTICLES
pp.3-10
An Architecture Design Methodology for Minimal Total Power
Consumption at Fixed Vdd and Vth
Christian Schuster, Christian Piguet, Jean-Luc Nagel, and
Pierre-André Farine
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp.11-19 Selective Clock-Gating for
Low-Power Synchronous Counters
Pilar
Parra, Antonio J. Acosta, Raúl Jiménez, and Manuel
Valencia
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp.20-26 Compact and Secured
Primitives for the Design of Asynchronous Circuits
A.
Razafindraibe, M. Robert, and P. Maurine
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp.27-43 Frame-Based Dynamic Voltage
and Frequency Scaling for an MPEG Player
Kihwan Choi,
Wei-Chung Cheng, and Massoud Pedram
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp.44-51 Energy-Aware MPEG-4 FGS
Streaming
Kihwan Choi, Kwanho Kim, and Massoud Pedram
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp.52-62 Low-Energy
Heterogeneous Non-Volatile Memory Systems for Mobile Systems
Hyung
Gyu Lee and Naehyuck Chang
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp.63-72 Selecting
Error Correcting Codes to Minimize Power in Memory Checker
Circuits
Shalini Ghosh, Sugato Basu, and Nur A.Touba
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp.73-84 Power and
Design for Test: A Design Automation Perspective
Aurelia
De Colle, Sanjay Ramnath, Mokhtar Hirech, and Subramanian Chebiyam
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
pp.85-95 Low Power
Scan Chain Design: A Solution for an Efficient Tradeoff Between
Test Power and Scan Routing
Patrick Girard and Yannick
Bonhomme
[Abstract]
[Full
Text - PDF] [Full
Text - RealPage] [Purchase
Article]
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